1. Field of the Invention
The present invention relates to a current cell type of digital-to-analog converter, in particular, to such a converter having a group of constant current cells producing even constant currents therebetween in dependent upon a digital signal.
2. Description of the Background Art
Reference will be made to FIGS. 2 to 5 for describing a conventional current cell type of digital-to-analog converter for better understanding the present invention. FIG. 2 is a schematic block diagram showing a conventional current cell type of digital-to-analog converter 100, which comprises a constant current cell group 2 having a plurality of constant current cells arranged in a matrix array for delivering constant currents in accordance with a bias voltage VB applied from a bias voltage generator 1, a switch group 3 having a plurality of switches for differentially selecting the currents output from the constant current cells to thereby output the selected currents, a switch controller 4 for controlling the switches of switch group 3 in response to an input digital signal DS, and a current-to-voltage converter 5 for converting the currents output from the switch group 3 to a corresponding analog voltage AV.
FIG. 3 is a schematic circuit diagram showing an example of conventional constant current cell group and switch group for use in such a current cell type of digital-to-analog converter. In the following, like structural parts or elements will be designated by identical reference numerals, and not repetitively be described in order to avoid redundancy.
In FIG. 3, the constant current cell group 2 comprises a plurality of constant current cells U, a MOS (Metal-Oxide Semiconductor) capacitance C and dummy transistors D. Each of the constant current cells U consists of a MOS transistor, which has its source electrode connected in common to a power supply voltage VDD and its gate electrode connected in common to be supplied with a common bias voltage VB, thereby allowing its drain electrode to output a constant current in dependent upon the bias voltage VB. The MOS capacitance C consists of a MOS transistor which has its source and drain electrodes connected to the power supply voltage VDD, and its gate electrode connected in common to the gate electrode of the constant current cells U. The MOS capacitance C has its gate capacitance thus inserted between the gate electrode of the constant current cells U and the power supply voltage VDD to thereby prevent the gate potential on the constant current cells U from varying. The dummy transistors D consist of unused MOS transistors placed around the constant current cells U, which will be described later.
The switch group 3 comprises a plurality of switches SW which correspondingly interconnected to the constant current cells U of the constant current cell group 2. Each switch SW comprises a first and a second MOS transistor which are interconnected so as to have the conduction state thereof controllable complementarily therebetween in response to control signals CON fed separately from each other by the switch controller 4, FIG. 2. The first and second MOS transistors of each switch SW have the source electrode thereof connected to the drain electrode of the corresponding constant current cell U. Also, the first and second MOS transistors of each switch SW have their drain electrodes connected in common to nodes N1 and N2, respectively. The sum of the currents flowing through the first MOS transistors and the sum of the current flowing the second MOS transistors of the entire switches SW are respectively supplied from the nodes N1 and N2 to the current-to-voltage converter 5.
Now, FIG. 4 schematically shows an example of layout of the constant current cell group 2 shown in FIGS. 2 and 3, more specifically, shows how the electrodes of the constant current cells, the MOS capacitances and the dummy transistors are formed and structured.
In FIG. 4, the constant current cells U, the MOS capacitances C and the dummy transistors D of the constant current cell group 2 consist of the MOS transistors formed in the identical configuration and are arranged in a matrix array as illustrated in the figures. In the illustrative example, the MOS capacitances C are formed in the left two rows in the figure, and on the right of the MOS capacitances C, the constant current cells U and the dummy transistors D are formed. The constant current cells U are arranged on the inner part of the matrix array and surrounded by the dummy transistors D.
The dummy transistors D are adapted to equalize the properties of the constant current cells U arranged inward with respect to the dummy transistors. That is to say, in manufacturing process of the MOS transistors of the identical configuration arranged in the matrix array, small differences in diffusion concentration and temperature distribution of, e.g. process gas used may cause slight difference in size between the gate electrodes formed in the MOS transistors disposed on the inner part where the array pattern thereof is dense and the MOS transistors on the peripheral part where the array pattern is sparse, thereby causing a difference in their properties. Thus, the MOS transistors on the peripheral part are disposed as the dummy transistors D which are never utilized whereas the MOS transistors on the inner part of the matrix will be made active to be served as the constant current cells U so as to supply constant currents uniform between the cells U.
FIG. 5 is an enlarged, conceptual view of apart enclosed in FIG. 4 with the chain-lined rectangle A. As shown in FIG. 5, the constant current cells U have the gate electrodes connected via contact pads to metal strips Ml to which the common bias voltage VB is applied, source electrodes connected via a contact pad to the power supply voltage VDD and drain electrodes connected through a contact pad to the corresponding switches SW of the switch group. In FIG. 5, wirings for the power supply voltage VDD and the switches SW are not shown.
The MOS capacitance C have their gate electrodes connected to the metal strips M1 through contact pads, while having their source and drain electrodes connected via contact pads to the power supply voltage VDD. It is to be noted that source, gate and drain electrodes of the dummy transistors D have no electrical connections.
In such a current cell type of digital-to-analog converter, each constant current cell U of the constant current cell group 2 produces stable and even current to supply it to the switch SW of the switch group 3 corresponding to the cell. In each switch SW of the switch group 3, the first or second MOS transistor of the switch SW is turned on by the control signal CON output from the switch controller 4 in response to a digital signal DS, whereby each switch SW carries a constant current fed from each constant current cell U regardless of the presence or absence of the control signal CON. The currents passing through the first and second MOS transistors in each switch SW are added up at the nodes N1 and N2, respectively, so that the sums of the currents are delivered to the current-to-voltage converter 5.
When the group of switches 2 includes m switches SW in total, where m is a natural number more than unity, and one or ones (n) of the m switches SW has/have the first MOS transistors turned ON, the total amount of currents flowing from the first MOS transistors of the switch group 3 to the node N1 is n times as much as the constant currents passing through the constant current cells U. Furthermore, the total amount of currents flowing from the second MOS transistors of the switch group 3 to the node N2 is (m−n) times as much as the constant currents passing through the constant current cells U. The currents sent out from the nodes N1 and N2 of the switch group 3 are converted to analog voltage outputs AV by the current-to-voltage converter 5 and output therefrom.
In the cell type of digital-to-analog converter, ones of the MOS transistors arranged in the periphery of the matrix array is rendered as unused dummy transistors and the MOS transistors on the inner part of the array serve as the constant current cells U. In addition, MOS transistors identical in configuration to the transistors U have the source and drain electrodes connected to the power supply voltage VDD, and the gate electrode connected to the gate electrodes of the constant current cells U so as to function as the MOS capacitances C. Therefore, the bias voltage VB can be stable, and thereby more even and stable constant current can be output. Accordingly, the digital-to-analog converter can supply an analog voltage AV with higher accuracy. Such a cell type of digital-to-analog converter is disclosed, for example, by Japanese patent laid-open publication No. 239059/1999.
However, the constant current cell group 2 of the current cell type of digital-to-analog converter involves such a drawback, specifically, that the gate electrodes of the constant current cells U of the constant current cell group 2 remain isolated, during the manufacturing process, from the semiconductor substrate or potential well. If, under such circumstances, the gate electrodes are made connected through the contact pads to the metal strip M1 and further processed by, e.g. plasma etching, then the electric charges thus injected are concentrated on the metal strips M1 or the equivalent to render the electric charges applied to the gate electrodes of the constant current cells U, that is so-called antenna effect. The antenna effect increases in proportion to an antenna ratio, i.e. the ratio of the metal wiring area connected to the gate region to the area of the gate region, thereby more deteriorating the gate insulating layer. Since the antenna ratio varies according to where the constant current cells U are arranged, the gate insulating layers of the constant current cells U are not evenly deteriorated. Consequently, the threshold voltage and drain current differ in magnitude constant current cell U by cell, thus rendering it difficult to produce constant currents which are even between the cells U.